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1/17 l6598 june 2004 1 features high voltage rail up to 600v dv/dt immunity 50v/ns in full temperature range driver current capability: 250ma source 450ma sink switching times 80/40ns rise/fall with 1nf load cmos shut down input under voltage lock out soft start frequency shifting timing sense op amp for closed loop control or protection features high accuracy current controlled oscillator integrated bootstrap diode clamping on vs so16, dip16 packages 2 description the device is manufactured with the bcd off line technology, able to ensure voltage ratings up to 600v, making it perfectly suited for ac/dc adapters and wherever a resonant topology can be benefi- cial. the device is intended to drive two power mos, in the classical half bridge topology. a dedicated timing section allows the designer to set soft start time, soft start and minimum frequency. an error amplifier, together with the two enable inputs, are made available. in addition, the integrated bootstrap diode and the zener clamping on low voltage sup- ply, reduces to a minimum the external parts needed in the applications. high voltage resonant controller figure 2. block diagram gnd v ref ifmin rfmin vco en1 vthe1 vthe2 en2 v s v boot out c boot load h.v. lvg uv detection vs hvg bootstrap driver hvg driver lvg driver css v ref ifstart rfstart cf op amp + - opout opin- opin+ dead time driving logic control logic iss + - + - level shifter d98in887a 12 5 6 7 4 2 3 1 9 8 10 11 14 15 16 fi gure 1. p ac k ages table 1. order codes part number package l6598 dip-16 l6598d so-16n L6598D013TR tape & reel dip-16 so-16n
l6598 2/17 figure 3. pin connection table 2. thermal data table 3. pin function symbol parameter so16n dip16 unit r th j-amb thermal resistance junction to ambient 120 80 c/w n. name function 1c ss soft start timing capacitor 2r fstart soft start frequency setting - low impedance voltage source - see also c f 3c f oscillator frequency setting - see also r fmin , r fstart 4r fmin minimum oscillation frequency setting - low impedance voltage source - see also c f 5op out sense op amp output - low impedance 6op on- sense op amp inverting input - high impedance 7op on+ sense op amp non inverting input - high impedance 8 en1 half bridge latched enable 9 en2 half bridge unlatched enable 10 gnd ground 11 lvg low side driver output 12 v s supply volatge with internal zener clamp 13 n.c. not connected 14 out high side driver reference 15 hvg high side driver output 16 v boot bootstrapped supply voltage css rfstart cf rfmin opout opin+ opin- 1 3 2 4 5 6 7 gnd v s lvg n.c. out hvg vboot 16 15 14 13 12 10 11 en1 8 en2 9 d98in888
3/17 l6598 table 4. absolute maximum ratings (*) the device is provided of an internal clamping zener between gnd and the vs pin, it must not be supplied by a low impedance voltage source. note : esd immunity for pins 14, 15 and 16 is guaranteed up to 900 (human body model). table 5. recommended operating conditions (*) if the condition vboot - vout < 18 is guaranteed, vout can range from -3 to 580v. symbol parameter value unit i s supply current at v cl (*) 25 ma v lvg low side output 14.6 v v out high side reference -1 to v boot -18 v v hvg high side output -1 to v boot v v boot floating supply voltage 618 v dv boot/dt vboot pin slew rate (repetitive) 50 v/ns dv out/dt out pin slew rate (repetitive) 50 v/ns v ir forced input voltage (pins rfmin, rfstart) -0.3 to 5 v v ic forced input volatge (pins css, cf) -0.3 to 5 v v en1 , v en2 enable input voltage -0.3 to 5 v i en1 , i en2 enable input current 3 ma v opc sense op amp common mode range -0.3 to 5 v v opd sense op amp differential mode range -5 to 5 v v opo sense op amp output voltage (forced) 4.6 v t stg storage temperature -40 to +150 c t j junction temperature -40 to +150 c t amb ambient temperature -40 to +125 c symbol parameter value unit v s supply voltage 10 to v cl v v out (*) high side reference -1 to vboot-v cl v v boot (*) floating supply rail 500 v f max maximum switching frequency 400 khz
l6598 4/17 table 6. electrical characteristcs (v s = 12v; v boot - v out = 12v; t amb = 25c) symbol pin parameter test condition min. typ. max. unit supply voltage v suvp 12 v s turn on threshold 10 10.7 11.4 v v suvn v s turn off threshold 7.3 8 8.7 v v suvh supply voltage under voltage hysteresis 2.7 v v cl supply voltage clamping 14.6 15.6 16.6 v i su start up current v s < v suvn 250 a i q quiescent current, fout = 60khz, no load v s > v suvp 23ma high voltage section i bootleak 16 boot pin leakage current v boot = 580v 5 a i outleak 14 out pin leakage current v out = 562v 5 a r don 16 bootstrap driver on resistance 100 150 300 ? high/low side drivers i hvgso 15 high side driver source current v hvg -v out = 0 170 250 ma i hvgsi high side driver sink current v hvg -v boot = 0 300 450 ma i lvgso 11 low side driver source current v lvg-gnd = 0 170 250 ma i lvgsi low side driver sink current v lvg - v s = 0 300 450 ma t rise 15,11 low/high side output rise time c load = 1nf 80 120 ns t fall c load = 1nf 40 80 ns oscillator dc 14 output duty cycle 48 50 52 % f min minimum output oscillation frequency c f = 470pf; r fmin = 50k 58.2 60 61.8 khz f start soft start output oscillation frequency c f = 470pf; r fmin = 50k; r fstart = 47k 114 120 126 khz v ref 2, 4 voltage to current converters threshold 1.922.1v t d 14 dead time between low and high side conduction 0.2 0.27 0.35 s timing section k ss 1 soft start timing constant c ss = 330nf 0.115 0.15 0.185 s/ f sense op amp l ib 6, 7 input bias current 0.1 a v io input offset voltage -10 10 mv r out 5 output resistance 200 300 ? i out- source output current v out = 4.5v 1 ma i out+ sink output current v out = 0.2v 1 ma v ic 6,7 op amp input common mode range -0.2 3 v
5/17 l6598 (*) guaranted by design figure 4. en2 timing diagrams figure 5. en1 timing diagrams gbw sense op amp gain band width product (*) 0.5 1 mhz g dc dc open loop gain 60 80 db comparators v the1 8 enabling comparator threshold 0.56 0.6 0.64 v v the2 9 enabling comparator threshold 1.05 1.2 1.35 v t pulse 8,9 minimum pulse lenght 200 ns table 6. electrical characteristcs (continued) (v s = 12v; v boot - v out = 12v; t amb = 25c) symbol pin parameter test condition min. typ. max. unit v s t ss f start f min en2 v css f out t ss d98in88 9 en1 en2 lvg hvg d98in890
l6598 6/17 figure 6. oscillator/output timing diagram 3 block?s diagram description 3.1 high/low side driving section an high and low side driving section provide the proper driving to the external power mos or igbt. an high sink/source driving current (450/250 ma typ) ensure fast switching times also when size4 power mos are used. the internal logic ensures a minimum dead time to avoid cross-conduction of the power devices. 3.2 timing and oscillator section the device is provided of a soft start function. it consists in a period of time, t ss , in which the switching frequen- cy shifts from f start to f min . this feature is explained in the following description (ref. fig.7 and fig.8). figure 7. soft start and frequency shifting block lvg hvg c f d98in897 css ifmin ifstart iss gm osc iosc
7/17 l6598 during the soft start time the current i ss charges the capacitor c ss , generating a voltage ramp which is delivered to a transconductance amplifier, as shown in fig. 7. thus this voltage signal is converted in a growing current which is subtracted to i fstart . therefore the current which drives the oscillator to set the frequency during the soft start is equal to: [1] where [2] at the start-up (t=0) the oscillator frequency is set by: [3] at the end of soft start (t = t ss ) the second term of eq.1 decreases to zero and the switching frequency is set only by i min (i.e. r fmin ): [4] since the second term of eq.1 is equal to zero, we have: [5] note that there is not a fixed threshold of the voltage across c ss in which the soft start finishes (i.e. the end of the frequency shifting), and t ss depends on c ss , i fstart , g m , and i ss (eq. 5). making t ss independent of i fstart , the i ss current has been designed to be a fraction of i fstart , so: [6] in this way the soft start time depends only on the capacitor c ss . the typical value of the k ss constant (soft start timing constant) is 0.15 s/ f. the current i osc is fed to the oscillator as shown in fig. 7. it is twice mirrored (x4 and x8) generating the triangular wave on the oscillator capacitor c f . referring to the internal structure of the oscillator (fig.7), a good relationship to compute an approximate value of the oscillator frequency in normal operation is: [7] the degree of approximation depends on the frequency value, but it remains very good in the range from 30khz to 100khz (figg.9-13) i osc i fmin i fstart g m v css t () ? () + i fmin i fstart g m i ss c ss -------------- t ? ?? ?? + == i fmin v ref r fmin -------------- i fsart , v ref r fstart ---------------- v ref , 2v == = i osc 0 () i fmin i fstart + v ref 1 r fmin ------------- - 1 r fstart ---------------- + ?? ?? == i osc t ss () i fmin v ref r fmin -------------- == i fstart g m i ss c ss -------------- t ss ? 0t ss c ss i fstart g m i ss ----------------------- - == i ss i fstart k ------------- - t ss c ss i fstart g m i fstart k ------------------------- - t ss c ss g m k ----------- t ss k ss c ss ? == = f min 1.41 r fmin c f -------------------- =
l6598 8/17 figure 8. oscillator block x 8 x 4 iosc vth+ vth- s r cf + +
9/17 l6598 figure 9. typ. fmin vs. rfmin @ cf = 470pf figure 10. typ. (fstart-fmin) vs. rfstar @ cf = 470pf figure 11. typ. (fstart-fmin) vs. rfstar @ cf = 470pf figure 12. typ. (fstart-fmin) vs. rfstar @ cf = 470pf figure 13. fmin @ different rf vs cf 20 40 60 80 100 r fmin (k ? ) 20 40 60 80 100 f min (khz) d98in891 20 40 60 80 100 r fstart ( k ? ) 20 40 60 80 ? f (khz) rfmin=33k ? d98in892 20 40 60 80 100 r fstart (k ? ) 20 40 60 80 100 ? f (khz) rfmin=50k ? d98in893 20 40 60 80 100 r fstart (k ? ) 20 40 60 80 100 ? f (khz) rfmin=100k ? d98in894 cf (pf) 400 0 200 0 200 400 fmin (khz) rf=90kohm - calc. rf=19.9kohm - calc. rf=90kohm - meas. rf=19.9kohm - meas.
l6598 10/17 3.3 bootstrap section the supply of the high voltage section is obtained by means of a bootstrap circuitry. this solution normally re- quires an high voltage fast recovery diode for charging the bootstrap capacitor (fig. 14a). in the device a patent- ed integrated structure, replaces this external diode. it is realised by means of a high voltage dmos, driven synchronously with the low side driver (lvg), with in series a diode, as shown in fig. 14b. figure 14. bootstrap driver to drive the synchronised dmos it is necessary a voltage higher than the supply voltage vs. this voltage is obtained by means of an internal charge pump (fig. 14b). the diode connected in series to the dmos has been added to avoid undesirable turn on of it. the introduction of the diode prevents any current can flow from the v boot pin to the v s one in case that the supply is quickly turned off when the internal capacitor of the pump is not fully discharged. the bootstrap driver introduces a voltage drop during the recharging of the capacitor c boot (i.e. when the low side driver is on), which increases with the frequency and with the size of the external power mos. it is the sum of the drop across the r dson and of the diode threshold voltage. at low frequency this drop is very small and can be neglected. anyway increasing the frequency it mu st be taken in to account. in fact the drop, reducing the amplitude of the driving signal, can significantly increase the r dson of the external power mos (and so the dissipation). to be considered that in resonant power supplies the cu rrent which flows in the power mos decreases increas- ing the switching frequency and generally the increases of r dson is not a problem because power dissipation is negligible. the following equation is useful to compute the drop on the bootstrap driver: [8] where q g is the gate charge of the external power mos, r dson is the on resistance of the bootstrap dmos, and t charge is the time in which the bootstrap driver remains on (about the semiperiod of the switching frequency minus the dead time). the typical resistance value of t he bootstrap dmos is 150 ohm. for example using a power mos with a total gate charge of 30nc the drop on the bootstrap driver is about 3v, at a switching fre- quency of 200khz. in fact: to summarise, if a significant drop on the bootstrap driver (at high switching frequency when large power mos are used) represents a problem, an external di ode can be used, avoiding the drop on the r dson of the dmos. v s v boot lvg c boot v out v s v boot c boot v out d boot ab v drop i ch e arg r dson v diode v drop + q g t ch e arg ------------------- r dson v diode + == v drop 30nc 2.23 s ------------------ 150 ? 0.6v~2.6v + =
11/17 l6598 3.4 op amp section the integrated op amp is designed to offer low output impedance, wide band, high input impedance and wide common mode range. it can be readily used to implement protec tion features or a closed loop control. for this purpose the op amp output can be properly connected to r fmin pin to adjust the oscillation frequency. 3.5 comparators two cmos comparators are available to perform protec tion schemes. short pulses (>= 200ns) on comparators input are recognised. the en1 input (activ e high), has a threshold of 0.6v (typical value) forces the device in a latched shut down state (e.g. lvg low, hvg low, oscillator stopped), as in the under voltage conditions. nor- mal operating conditions are resumed after a power-off power-on sequence. the en2 input (active high), with a threshold of 1.2v (typical value) restarts a soft start sequence (see timing diagrams). in addition the en2 comparator, when activated, removes a latched shutdown caused by en1. figure 15. switching time waveform definitions figure 16. dead time and duty cycle waveform definition 90% 90% 10% 10% t f t r lvg 90% 90% 10% 10% t f t r hvg d98in898 lvg hvg t d 50% 50% t d 50% 50% t 1 50% t period dc = t period t 1 d98in899
l6598 12/17 figure 17. typ. fmin vs. temperature figure 18. typ. fstart vs. temperature figure 19. vs thresholds and clamp vs temp. figure 20. start up current vs temperature figure 21. quiescent current vs temperature figure 22. hvg source and sink current vs. temperature -50 0 50 100 40 50 60 70 t ( ?c ) f min (khz) d98in895 -50 0 50 100 100 110 120 130 t(?c) f fstart (khz) d98in896 vs (v) t (c) -50 0 50 100 6 8 10 12 14 vclamp vsuvp vsuvn -50 050 100 100 50 150 200 isu ( a) t (c) -50 0 50 100 t (c) 2.3 2.1 1.9 1.7 1.5 iq @ 12v iq @ vclamp iq (ma) -50 050 100 t (c) 200 300 100 400 500 ihvg source curr. ihvg sink curr. ihvg (ma)
13/17 l6598 figure 23. lvg source and sink current vs. temperature figure 24. soft start timing constant vs. temperature 200 300 100 400 500 ilvg (ma) -50 050 100 t (c) ilvg source curr. ilvg sink curr. -50 050 100 t (c) 0.14 0.12 0.16 kss (s/ f) figure 25. wide range ac/dc adapter application l6561/2 85 to 270 vac vo tl431 vco & control driver l6598 enable d98in874a_mod2
l6598 14/17 figure 26. dip-16 mechanical data & package dimensions dip16 dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 d 20 0.787 e 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 f 7.1 0.280 i 5.1 0.201 l 3.3 0.130 z 1.27 0.050 outline and mechanical data
15/17 l6598 figure 27. so-16n mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 c 0.5 0.020 c1 45 (typ.) d (1) 9.8 10 0.386 0.394 e 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 f (1) 3.8 4.0 0.150 0.157 g 4.60 5.30 0.181 0.208 l 0.4 1.27 0.150 0.050 m 0.62 0.024 s8 (max.) (1) "d" and "f" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (.006inc.) so16 (narrow) 0016020 d
l6598 16/17 figure 28. revision history date revision description of changes june 2004 5 changed the impagination following the new release of ?corporate technical pubblication design guide?. done a few of corrections in the text.
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